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CONTENTS: |
The version of iammx.inc which is currently distributed with the Borland TASM assembler generates fatal errors for some instructions. This paper is a listing of a work around which will allow developers using TASM to generate opcodes for MMX (tm) technology instructions. Listed below are examples of the macro versions of instructions which are different than what you would use for MASM. Notice that there are multiple versions depending on whether the operator has memory, register, or immediate operands. Programmers should use the appropriate version depending upon the operands.
Download ibmmx.inc, the include file for TASM 5.0
Download icmmx.inc (may be required for versions of TASM older that 5.0)
.486p .MODEL flat include ibmmx.inc ;modified include file .DATA a dWORD 256 DUP (0) ;256/2 qwords .CODE main proc near ;TESTS OF THE MOVD INSTRUCTION movd1 eax, mm0 ; mmx -> 32x movd2 mm0, eax ; 32x -> mmx movd2 mm0, mm1 ; mmx -> mmx movd2 mm0, a ; MEM -> mmx movd2 mm0, [eax] ; MEM -> mmx movd3 [eax], mm0 ; mmx -> mem movd3 a, mm0 ; mmx -> mem ;TESTS OF THE MOVQ INSTRUCTION movq1 mm0, a ;mem to mmx movq2 [eax], mm0 ;mmx to mem movq2 a, mm0 ;mmx to mem movq1 mm0, [eax] ;mmx to mem movq1 mm1, mm0 ;mmx to mmx ;TESTS OF THE PSLLD INSTRUCTION pslld1 mm0, 1 ; mmx by imm pslld2 mm0, mm1 ; mmx by mmx pslld2 mm0, eax ; mmx by 32x pslld2 mm0, a ; mmx by mem pslld2 mm0, [eax] ;TESTS OF THE PSLLW INSTRUCTION psllw1 mm0, 1 ; mmx by imm psllw2 mm0, mm0 ; mmx by mmx psllw2 mm0, eax ; mmx by 32x psllw2 mm0, a ; mmx by mem psllw2 mm0, [eax] ;TESTS OF THE PSLLQ INSTRUCTION psllq1 mm0, 1 ; mmx by imm psllq2 mm0, mm0 ; mmx by mmx psllq2 mm0, eax ; mmx by 32x psllq2 mm0, a ; mmx by mem psllq2 mm0, [eax] ;TESTS OF THE PRAD INSTRUCTION psrad1 mm1, 1 ; mmx by imm psrad2 mm1, mm0 ; mmx by mmx psrad2 mm1, eax ; mmx by 32x psrad2 mm1, a ; mmx by mem psrad2 mm0, [eax] ;TESTS OF THE PRAW INSTRUCTION psraw1 mm1, 1 ; mmx by imm psraw2 mm1, mm0 ; mmx by mmx psraw2 mm1, eax ; mmx by 32x psraw2 mm1, a ; mmx by mem psraw2 mm0, [eax] ;TESTS OF THE PSRLW INSTRUCTION psrlw1 mm1, 1 ; mmx by imm psrlw2 mm1, mm0 ; mmx by mmx psrlw2 mm1, eax ; mmx by 32x psrlw2 mm1, a ; mmx by mem psrlw2 mm0, [eax] ;TESTS OF THE PSRLD INSTRUCTION psrld1 mm1, 1 ; mmx by imm psrld2 mm1, mm0 ; mmx by mmx psrld2 mm1, eax ; mmx by 32x psrld2 mm1, a ; mmx by mem psrld2 mm0, [eax] ;TESTS OF THE PSRLQ INSTRUCTION psrlq1 mm1, 1 ; mmx by imm psrlq2 mm1, mm0 ; mmx by mmx psrlq2 mm1, eax ; mmx by 32x psrlq2 mm1, a ; mmx by mem psrlq2 mm0, [eax] main endp END main